IEAN/Service and infrastructure/Laboratory equipment

With our network model and the associated peripherals such as transformers, overhead lines, network protection devices and distributors, extensive experimental setups and simulations in the field of electrical systems and networks are possible.

PHILlab

PHILlab (Power-Hardware-in-the-Loop Laboratory)
The PHILlab at the Institute of Electrical Power Systems is used for research projects and services for project partners and works on the basis of state-of-the-art technology, Hardware-In-the-Loop.

 
Figure 1: PHILlab at the Institute for Electrical Power Systems

The infrastructure of the PHILlab provides a unique research environment for Controller-Hardware-in-the-Loop (CHIL) and Power-Hardware-in-the-Loop (PHIL).

CHIL infrastructure:

  • 2x FPGAs - NI sbRIO-9607
  • 2x FPGAs - Zedboard
  • StarSim real-time computer
  • dSpace - SCALEXIO real-time computer

PHIL infrastructure:

  • 2x grid simulators with 30kVA each
    • 0 HZ to 1 kHz fundamental frequency
    • Up to 5 kHz harmonic
    • up to ± 400 V 3-phase
    • up to 43 A
  • B2B converter with 10 kVA – Free programmable FPGA
  • 60 kVA transformer
    • Voltage ratio - primary:secondary - 1:1
    • selectable vector group
  • 3x 10 kW power resistors
  • 4x 1200 W power resistors

High Voltage Test Cell

The IEAN has a high voltage test cell that can be operated from the 400 V mains or with two power amplifiers.

Spatial dimensions: 2.70 m x 2.50 m (width x depth); passage: 1 m x 1.90 m (width x depth)

Power:

  • PHIL:
    • Parallel Operation: 3 x 305 VRMS, 86 A, 60 kVA, 0 – 1 kHz, 0 – 5 kHz (modulation bandwidth), DC Offset < 10 mV
    • Single Operation: 3 x 305 VRMS, 43 A, 30 kVA, 0 – 1 kHz, 0 – 5 kHz (modulation bandwidth), DC Offset < 10 mV
  • Mains Connection: 3 x 230 VRMS, 63 A, 43,5 kVA
  • Transformers:
    • Freely selectable vector group on the low voltage level; high voltage level: YN
    • 0,4/35 kVRMS, L-L, 72,1 A, 50 kVA

 

Measurements and Tests:

  • Short Circuit Test (up to rated currents of 86 A/phase)
  • Induced AC voltage test up to 300 VRMS on the low voltage level
  • Back-to-Back Tests
  • Superimposed DC via high voltage neutral start point
  • Superimposed low frequency currents on individual low voltage phases


    Figure 1: High voltage test cell at IEAN