Current Research Projects

Harmonic distortion are unwanted electromagnetic disturbances of the electrical system. There are requirements of the EU to minimize these disturbances. Especially for antenna ESD protection devices, and to a lesser extent for other ESD protection applications, this is an important device parameter.

- Development of prototypes
- Measures at circuit board level, taking mechanical aspects into account
- EMC compliance measurements
- Design of analogue circuits (e.g. power management, DC-DC converters, sensor-actuator systems, high-precision amplifiers ...)
- Design of mixed-signal circuits (precision measurement technology, ADC, DAC, ...)
- Design of digital filters, DSP systems, ...
- Application of analogue and digital control technology
- EMC-compliant design and layout
- EMC review of circuit diagrams and layouts
- Scientific evaluation of measurement results

The diploma thesis entitled "An Advanced High Current Stress Test System for Automotive Power Switches" is completed.

The CDL conducts fundamental research in Electromagnetic Compatibility which includes emission, immunity, and ESD to develop robust electronic systems. The main areas of application are automotive power converters, smart power devices, detection and analysis of damaging electrostatic discharge and RF and antenna frontends of mobile devices. The research challenges worked on are the development of physical models and therefrom training of machine learning (ML) models. Other ML models will be constructed from measurements. The ML models will be used for parameter studies, risk analysis, optimization, and model calibration.

The goal of the project is to combine electromagnetic full-wave simulation with high-voltage corona and spark simulation. This multi-physics approach will be verified by sets of experiments that vary critical parameters along the parameter ranges covered by electrostatic discharges and corona discharges along dielectric surfaces with and without metal backing.

Investigation of ESD partial discharge processes on plastic housings of micromechanical sensor devices.

The main focus of the work is on the lifetime evaluation of two-dimensional, resonant microelectromechanical mirrors.

The one contact harmonic test system is being tested in this project.

This SOW applies to University’s research services on ESD Threat Assessment; Improving methods and simulations for quality testing beyond regulatory requirements; SEED Analysis; and Quantifying and reproducing the rock tumbler as an ESD source.

Ionizing radiation, like X- and gamma rays, cause a gradual damage in semiconductor devices. Radiationinduced defects build up throughout the exposure time leading to change of transistor characteristics. This leads to reliability issues in integrated circuits (IC). Over the years scaling of the integrated circuit process improved the robustness to radiation thanks to thinner silicon oxides under MOS transistor gate and higher bulk doping levels. However, starting with 40 nm and 28 nm process nodes to reduce high gate leakage currents the gate material had to change to one with high-dielectric constant. This new gate stack in combination with aggressive scaling is expected to uncover new radiation effects. The project SIRENS will focus on these modern process nodes and examine device-level effects and mechanisms of defects forming due to X-rays. Custom integrated test circuits in 40 nm and 28 nm processes will be designed. These will include dedicated test structures, above all arrays of different size and type transistors. Test structures will be exposed to X-ray radiation to characterize parameters drift. Also energy and spatial distributions of traps in the new gate stack will be studied. The effects will be examined from three perspectives. First, the transistor geometry ependence will be examined. The reason of the apparent lack of radiation induced narrow channel effect in p-channel MOS transistor will be investigated. The radiation-induced short channel effect will be examined to determine the dominating effect amongst the three hypotheses: of charge trapping in sidewall spacer, of halo implant increasing the effective doping, and of gate extension area influencing the electric field. The second perspective covers examination of the extent of possible radiation damage. For this, the evolution of traps density will be evaluated up to very high total ionizing dose levels, reaching 1 Grad, including annealing. The final third aspect is studies of dose rate sensitivity of MOS transistors. The hypothesis, suggested in several recent papers, states that high dose rate in accelerated X-ray testing could lead to illusionary lower damage effects than the stress with low dose rate. Today’s understanding of radiation effects in scaled devices down to 28 nm process is only superficial. The proposed studies encompassing two process nodes (40 nm and 28 nm) and three foundries (Fab40, Fab28- A and Fab28-B) will greatly enrich the state of the current knowledge.