Current Research Projects

Evaluation and assessment of malfunctions of operated Smart Power ASICs during ESD gunshot tests. Development of measurement methods, laboratory analyses and design measures for robust design.

The AT-C³ is designed as the “Austrian Chip Design & Prototyping Support Center”, set up as a consortium by 6 leading organizations of the Austrian semiconductor ecosystem. USP (focus areas): The AT-C³ has designed a comprehensive program to strengthen the European semiconductor industry. It includes expertise for the development of advanced materials, thin film technologies and quantum & photonics applications. Additional national core expertise in Analog Mixed Signal Design, Power Electronics, Advanced Packaging & System Integration und Secure Connectivity & Communications will be ensured by many regional partners. Objectives and innovation content: The main objective of the AT-C³ is to play a leading role in providing expertise in the above mentioned focus areas. It will serve as a "one-stop store" for industry and research in Austria to facilitate access to the European network of chip pilot lines, the design platform, the ENCCC and the Chips Fund. In addition, it is intended to promote innovation and skills in Austrian start-ups, SMEs and large companies along the ESBS value chain and strengthen the international competitiveness of Austrian companies. Over 50% of the funds are to flow into SME/start-up specific measures and programs. Intended results and findings: The AT-C³ plans to build a community of practice for sustainable exchange, roughly 60 expertise projects, more than 70 support measures and an open access to relevant education and training programs primarely for SMEs and start-ups in the focus areas. It is expected that by providing access to pilot lines, design platform and expertise, as well as training and education programs, the gap in qualified professionals will be closed and the development of new technologies and products will be accelerated. In addition, special attention will be paid to the inclusion of gender and diversity aspects as well as the promotion of sustainability and climate neutrality in all AT-C³ activities.

As a contribution to the EU Chips Act, the Research Fab Microelectronics Germany (FMD) proposes an Advanced Packaging and Heterogeneous Integration for Electronic Components and Systems Pilot Line (APECS-PL), which combines the generation of globally competitive high technology that addresses the specific needs of German and European industry and enables a low-threshold, easily scalable industrial transfer. The APECS-PL will include novel characterization, quality assurance, testing & reliability methodologies, test methods to assess the security of microelectronic systems against physical attacks and a System Technology Co Optimization (STCO) framework. Together with the 2 nm GAA (imec), 5 nm FDSOI (Leti) and wide bandgap semiconductor pilot lines also planned within the EU Chips Act, the APECS-PL is also in a position to become an essential component on the way to the vision of a pan-European pilot line facility - and thus an indispensable pillar for achieving the EU Chips Act target of bringing 20% of the global supply of chip production back to Europe. In addition, APECS-PL offers a one-stop shop for a very broad international customer base in basically all classic vertical industrial sectors including large companies, SMEs and technology start-ups. Demonstrators are planned to evaluate how the elements of the pilot line work together.

As a contribution to the EU Chips Act, the Research Fab Microelectronics Germany (FMD) proposes an Advanced Packaging and Heterogeneous Integration for Electronic Components and Systems Pilot Line (APECS-PL), which combines the generation of globally competitive high technology that addresses the specific needs of German and European industry and enables a low-threshold, easily scalable industrial transfer. The APECS-PL will include novel characterization, quality assurance, testing & reliability methodologies, test methods to assess the security of microelectronic systems against physical attacks and a System Technology Co Optimization (STCO) framework. Together with the 2 nm GAA (imec), 5 nm FDSOI (Leti) and wide bandgap semiconductor pilot lines also planned within the EU Chips Act, the APECS-PL is also in a position to become an essential component on the way to the vision of a pan-European pilot line facility - and thus an indispensable pillar for achieving the EU Chips Act target of bringing 20% of the global supply of chip production back to Europe. In addition, APECS-PL offers a one-stop shop for a very broad international customer base in basically all classic vertical industrial sectors including large companies, SMEs and technology start-ups. Demonstrators are planned to evaluate how the elements of the pilot line work together.

Harmonic distortion are unwanted electromagnetic disturbances of the electrical system. There are requirements of the EU to minimize these disturbances. Especially for antenna ESD protection devices, and to a lesser extent for other ESD protection applications, this is an important device parameter.

- Development of prototypes
- Measures at circuit board level, taking mechanical aspects into account
- EMC compliance measurements
- Design of analogue circuits (e.g. power management, DC-DC converters, sensor-actuator systems, high-precision amplifiers ...)
- Design of mixed-signal circuits (precision measurement technology, ADC, DAC, ...)
- Design of digital filters, DSP systems, ...
- Application of analogue and digital control technology
- EMC-compliant design and layout
- EMC review of circuit diagrams and layouts
- Scientific evaluation of measurement results

The diploma thesis entitled "An Advanced High Current Stress Test System for Automotive Power Switches" is completed.

The CDL conducts fundamental research in Electromagnetic Compatibility which includes emission, immunity, and ESD to develop robust electronic systems. The main areas of application are automotive power converters, smart power devices, detection and analysis of damaging electrostatic discharge and RF and antenna frontends of mobile devices. The research challenges worked on are the development of physical models and therefrom training of machine learning (ML) models. Other ML models will be constructed from measurements. The ML models will be used for parameter studies, risk analysis, optimization, and model calibration.

The goal of the project is to combine electromagnetic full-wave simulation with high-voltage corona and spark simulation. This multi-physics approach will be verified by sets of experiments that vary critical parameters along the parameter ranges covered by electrostatic discharges and corona discharges along dielectric surfaces with and without metal backing.

The main focus of the work is on the lifetime evaluation of two-dimensional, resonant microelectromechanical mirrors.

This SOW applies to University’s research services on ESD Threat Assessment; Improving methods and simulations for quality testing beyond regulatory requirements; SEED Analysis; and Quantifying and reproducing the rock tumbler as an ESD source.